This invention relates generally to read only memory (ROM) circutis and, more particularly, to metal oxide semiconductor (MOS) field effect transistor (FET) read only memory cells used in such circuits.
As is known in the art, ROM circuits include a plurality of ROM cells typically arranged in a matrix of rows and columns, each row of cells storing a word of binary data, each bit of the binary data being stored by each one of the column-arranged cells in the row. The binary data is stored by programming the array of cells with selected ones thereof having "transistor action", while the remaining cells are not formed with such "transistor action". The presence or absence of transistor action in a cell corresponds to a logical 1 or logical 0 condition, respectively, thus enabling the cell to be programmed into either a logical 1 or a logical 0 state, respectively. As described in MOS/LSI Design and Application, by Dr. William N. Carr and Dr. Jack P. Mize, published by McGraw-Hill Book Company (1972), beginning on page 196, by selective masking, during the fabrication process the array of MOS FET cells, those selected cells which are to have "transistor action" are provided with gate oxides of standard gate oxide thicknesses, whereas those cells where there is to be no "transistor action", are provided with excessively large gate oxide thicknesses. It is noted, however, that the formation, or non-formation, of transistor action can be accomplished by a variety of other techniques, such as, for example, active area removal or ion implantation into the unwanted transistor region to raise the transistor's voltage threshhold level required for inhibiting current conduction.
As is also known in the art, one type of MOS ROM array includes n-channel MOS transistors with: grounded source contact; gate electrodes of each row of transistors connected to a corresponding row of electrical conductors (i.e., a word line); and drain contacts of each column of such transistors coupled to an output source amplifier via a corresponding column electrical conductor (i.e., a bit line). A suitable positive voltage supply, such as the drain voltage supply (V.sub.DD), is electrically coupled to the drain contacts via the bit lines for a short period of time, generally referred to as a pre-charge cycle, in order to reduce power. That is, rather than have the drain contacts remain connected directly to the +V.sub.DD supply at all times, a pre-charge cycle is generally provided since, absent the pre-charge cycle, when an address is fed to the word decoder to enable a row of transistors, those cells being programmed with "transistor action" would electrically couple the power supply to ground thereby continually draining power from the supply. With a pre-charge cycle, however, the voltage supply is electrically decoupled from the supply voltage except when the ROM is to be read. More particularly, a ROM which operates with a pre-charge cycle generally includes a transition detector circuit which detects a change in the address fed to the ROM. In response to this address change, the transition detector circuit produces a pulse which electrically connects the drain contacts to the +V.sub.DD source during a short time duration with the result that the bit lines, because of the capacitance (C) between the bit lines and the grounded semiconductor substrate, store a charge substantially equal to Q=CV.sub.DD. Once the bit is charged to +V.sub.DD (logical 1), the word, or address, decoder is enabled, (having been disabled during the pre-charge cycle) and a selected row of cells is thus addressed. The n-channel transistors in the addressed row programmed to have "transistor action" will have their respective bit lines discharged towards ground potential (or 0 volts) and hence a logical 0 state will be sensed by the output sense amplifiers connected to these transistor's bit lines. On the other hand, the n-channel transistors in the addressed row not programmed to have "transistor action" will have the bit lines connected to them remain substantially at the +V.sub.DD voltage level stored on the bit line in response to the pre-charged pulse. Since, under such condition, there is no electrical path provided through these transistors for discharging the charged bit line to ground potential, a logical 1 will be sensed by the output sense amplifiers connected to the bit lines of these transistors. In either case, however, the voltage source is electrically decoupled from the cells except for the short period of time required during the charge phase of the pre-charge cycle.
Thus, with such arrangement, while the memory is able to store logical data, and while the pre-charge cycle and associated circuitry described above reduces the power requirements of the memory, such pre-charge cycle and associated circuitry reduces the operating speed of the memory and also reduces the storage caoacity of the ROM by reducing the area available on the ROM chip for memory cells.